A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce av...

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Bibliographische Detailangaben
Hauptverfasser: Yoshida, Yutaka, Kamei, Tatsuya, Hayase, Kiyoshi, Shibahara, Shinichi, Nishii, Osamu, Hattori, Toshihiro, Hasegawa, Atsushi, Takada, Masashi, Irie, Naohiko, Uchiyama, Kunio, Odaka, Toshihiko, Takada, Kiwamu, Kimura, Keiji, Kasahara, Hironori
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Energy consumption
Energy management
Finishing
Frequency conversion
Frequency estimation
Hardware
Read-write memory
System buses
System-on-a-chip
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Beschreibung
Zusammenfassung:A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm 2 die achieves a floating-point performance of 16.8GFLOPS
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373607