An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

A 275mm 2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm...

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Bibliographische Detailangaben
Hauptverfasser: Vangal, Sriram, Howard, Jason, Ruhl, Gregory, Dighe, Saurabh, Wilson, Howard, Tschanz, James, Finan, David, Iyer, Priya, Singh, Arvind, Jacob, Tiju, Jain, Shailendra, Venkataraman, Sriram, Hoskote, Yatin, Borkar, Nitin
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Frequency
Jacobian matrices
Microprocessors
Network-on-a-chip
Sleep
TECHNOLOGY
TEKNIKVETENSKAP
Tellurium
Tiles
Voltage
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Beschreibung
Zusammenfassung:A 275mm 2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2007.373606