Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies

Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies

A multi-gate CMOS technology for low-power applications with highly competitive digital performance is presented. Ring oscillators with metal gates and undoped fins are measured with high yield demonstrating the capability of large scale integration. An inverter delay of 15 ps and 0.5 nA/stage off-c...

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Hauptverfasser: Schruefer, K., von Arnim, K., Pacha, C., Berthold, J., Cleavelin, C.R., Schulz, T., Xiong, W., Patruno, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit optimization
CMOS process
CMOS technology
Delay
Digital circuits
Frequency
Instruments
Leakage current
Stress
Threshold voltage
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Beschreibung
Zusammenfassung:A multi-gate CMOS technology for low-power applications with highly competitive digital performance is presented. Ring oscillators with metal gates and undoped fins are measured with high yield demonstrating the capability of large scale integration. An inverter delay of 15 ps and 0.5 nA/stage off-current at V dd =1.2 V shows an improved leakage-performance trade-off compared to 65 nm low-standby power CMOS technologies. Scalability to 32 nm and beyond is shown.
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2007.378961