A 45nm Low-Cost LSTP CMOS Technology with full NCS/dual-damascene Cu interconnects

A 45nm Low-Cost LSTP CMOS Technology with full NCS/dual-damascene Cu interconnects

A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasi...

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Hauptverfasser: Sukegawa, K., Okuno, M., Ochimizu, H., Yamaji, M., Fukuda, M., Sanbonsugi, Y., Kudo, H., Yoshida, E., Mizushima, Y., Arita, T., Yamamoto, T., Shimoda, Y., Osawa, M., Yao, T., Futatsuya, H., Terahara, M., Tajima, M., Ogura, J., Oryoji, M., Sugimoto, K., Sakai, H., Sunayama, M., Watanabe, T., Shirasu, T., Kojima, M., Kurata, H., Tsukune, A., Ikeda, K., Futatsugi, T., Satoh, S., Kase, M., Sugii, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Costs
Design optimization
Dielectrics
Energy consumption
Leakage current
Lithography
MOSFET circuits
Random access memory
Transistors
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Beschreibung
Zusammenfassung:A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasized that this technology is cost-effective.
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2007.378960