Test Power IR Drop Closure Flow for NetComposer-I Platform Design

Test Power IR Drop Closure Flow for NetComposer-I Platform Design

Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power rel...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kifli, A., Chen, W.J., Chen, Y.W., Wu, K.C.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cities and towns
Design for testability
Energy consumption
Fluctuations
Image storage
Inductance
Noise generators
Packaging
Switches
Testing
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Beschreibung
Zusammenfassung:Power noise has become one of the main culprits in failing chips in SoC designs. As power consumption during scan test can be several times higher than during normal operation, it must be dealt with properly during implementation and testing stages. In this paper, we share some of the test power related experiences we gained through the development of NetComposer platform design. We demonstrate how good power analysis and DFT can help avoid potential power noise issue during test.
DOI:10.1109/VDAT.2007.373201