Correlating Wafer-Level TDDB Lifetime Projections to HTOL Gate-Oxide Failures

Correlating Wafer-Level TDDB Lifetime Projections to HTOL Gate-Oxide Failures

The power-law model provides a relatively good correlation between the wafer-level (WL) time-dependent dielectric breakdown (TDDB) test (highly accelerated) conducted on test structures and high-temperature operating life (HTOL) test (moderately accelerated) conducted on product. This is true when W...

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Bibliographische Detailangaben
Hauptverfasser: Akram Ditali, Le, H.A., Butler, D.L., Ingram, M., Ma, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Acceleration
Circuit testing
Extrapolation
Leakage current
Life estimation
Life testing
Performance evaluation
Stress
Temperature sensors
Voltage
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Beschreibung
Zusammenfassung:The power-law model provides a relatively good correlation between the wafer-level (WL) time-dependent dielectric breakdown (TDDB) test (highly accelerated) conducted on test structures and high-temperature operating life (HTOL) test (moderately accelerated) conducted on product. This is true when WL stress is configured identically to HTOL stress, and the difference in oxide area between the two devices under stress is taken into account for lifetime projections.
ISSN:1541-7026
1938-1891
DOI:10.1109/RELPHY.2007.369955