An Efficient Polynomial Multiplier in GF(2m) and its Application to ECC Designs

This paper discusses approaches that allow constructing efficient polynomial multiplication units. Such multipliers are the most important components of ECC hardware accelerators. The proposed hRAIK multiplication improves energy consumption, the longest path, and required silicon area compared to state of the art approaches. The authors use such a core multiplier to construct an efficient sequential polynomial multiplier based on the known iterative Karatsuba method. Finally, the authors exploit the beneficial properties of the design to build an ECC accelerator. The design for GF(2 233 ) requires about 1.4 mm 2 cell area in a 0.25mum technology and needs 80 musec for an EC point multiplication