Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

As an industrial practice, the functional coverage models are developed based on a high-level specification of the design under verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed enti...

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Bibliographische Detailangaben
Hauptverfasser: Shireesh Verma, Harris, I.G., Kiran Ramineni
Format: Tagungsbericht
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:As an industrial practice, the functional coverage models are developed based on a high-level specification of the design under verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2007.364407