FPGA-based generic neural network architecture

In this paper, we defined a generic architecture for the extraction phase of a multi layer neural network algorithm to be implemented on a Virtex-4 FPGA. This architecture can be applied to any multi layer neural network composed of a given number of layers and a given number of neurons in each laye...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chalhoub, N., Muller, F., Auguin, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Collaborative work Decoding Field programmable gate arrays Multi-layer neural network Neural networks Neurons Performance analysis Read-write memory Runtime Stochastic processes
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