FPGA-based generic neural network architecture

In this paper, we defined a generic architecture for the extraction phase of a multi layer neural network algorithm to be implemented on a Virtex-4 FPGA. This architecture can be applied to any multi layer neural network composed of a given number of layers and a given number of neurons in each layer. In addition this architecture enhances the density of the FPGA by supporting the two concepts of time multiplexing and partial dynamic reconfiguration. Several networks with different sizes were implemented based on this generic architecture. Based on those implementations, we'll analyse the performances of a virtex-4 via a multi layer neural network by analyzing the variation of the minimum period and the number of occupied resources. This work was made in collaboration with the NodBox company (thierry.fargas@nodbox.biz) and Xilinx company (jean-louis.brelet@xilinx.com).