A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rar...
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| creator | Sato, T. Kunitake, Y. |
| description | The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay |
| doi_str_mv | 10.1109/ISQED.2007.23 |
| format | Conference Proceeding |
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Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay</description><subject>Circuits</subject><subject>Clocks</subject><subject>Delay estimation</subject><subject>Design for manufacture</subject><subject>Design methodology</subject><subject>Design optimization</subject><subject>Flip-flops</subject><subject>Large scale integration</subject><subject>Logic design</subject><subject>Voltage</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>0769527957</isbn><isbn>9780769527956</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9jM1KAzEYRYM_YFu7dOUmL5Axv5N8uCozHS20iLSuSyb9IpGpHSZ10be3qHg3B86BS8id4IUQHB4W69d5XUjObSHVBRkJ0I4pCeaSjLktwUgLxl79B2dvyDTnD36eAnOWI_I4o-u07zukTZd61nSHnlZpCF_pSONhoJtTn4LvWOUz0hpzev_MP6FuVrfkOvou4_SPE_LWzDfVM1u-PC2q2ZIFadyRKeOsAOQSEEqnW9ci8hjatgzWGh2FEx4hhLhTwUivdlEE7az3TutQRq0m5P73NyHith_S3g-nrRYaOHD1DX6iR74</recordid><startdate>20070101</startdate><enddate>20070101</enddate><creator>Sato, T.</creator><creator>Kunitake, Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20070101</creationdate><title>A Simple Flip-Flop Circuit for Typical-Case Designs for DFM</title><author>Sato, T. ; Kunitake, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c258t-358719e029e9684b8bee0fcbb6c7754f181ae9ccfd3c52a3df1c487aa844c6f43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>Delay estimation</topic><topic>Design for manufacture</topic><topic>Design methodology</topic><topic>Design optimization</topic><topic>Flip-flops</topic><topic>Large scale integration</topic><topic>Logic design</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Sato, T.</creatorcontrib><creatorcontrib>Kunitake, Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sato, T.</au><au>Kunitake, Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Simple Flip-Flop Circuit for Typical-Case Designs for DFM</atitle><btitle>8th International Symposium on Quality Electronic Design (ISQED'07)</btitle><stitle>ISQED</stitle><date>2007-01-01</date><risdate>2007</risdate><spage>539</spage><epage>544</epage><pages>539-544</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>0769527957</isbn><isbn>9780769527956</isbn><abstract>The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. 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| identifier | ISSN: 1948-3287 |
| ispartof | 8th International Symposium on Quality Electronic Design (ISQED'07), 2007, p.539-544 |
| issn | 1948-3287 1948-3295 |
| language | eng |
| recordid | cdi_ieee_primary_4149090 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Clocks Delay estimation Design for manufacture Design methodology Design optimization Flip-flops Large scale integration Logic design Voltage |
| title | A Simple Flip-Flop Circuit for Typical-Case Designs for DFM |
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