A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rar...

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Bibliographische Detailangaben
Hauptverfasser: Sato, T., Kunitake, Y.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay
ISSN:1948-3287
1948-3295
DOI:10.1109/ISQED.2007.23