An Efficient Implementation of Constrained Partitioned Processor for Broadband Antenna Array Without Steering Delays

A constrained partition processor is an implementation of a broadband time domain antenna array processor using a fixed main beam steered in the look direction and a set of auxiliary beams to remove unwanted directional noise from the main beam. The weights of the auxiliary beams are constrained to...

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Bibliographische Detailangaben
Hauptverfasser: Jahromi, M.R.S., Godara, L.C.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:A constrained partition processor is an implementation of a broadband time domain antenna array processor using a fixed main beam steered in the look direction and a set of auxiliary beams to remove unwanted directional noise from the main beam. The weights of the auxiliary beams are constrained to block the desired signal. This paper presents a scheme to estimate the weights of the auxiliary beams requiring much less computation time than existing techniques
ISSN:2159-3442
2159-3450
DOI:10.1109/TENCON.2006.343900