A CMOS Power Amplifier using Ground Separation Technique

This work presents an on-chip ground separation technique for power amplifiers. The ground separation technique is based on separating the grounds of the amplifier stages on the chip and thus any parasitic feedback paths are removed. Simulation and experimental results show that the technique makes the amplifier less sensitive to bondwire inductance, and consequently improves the stability and performance. A two-stage CMOS RF power amplifier for WCDMA mobile phones is designed using the proposed on-chip ground separation technique. The power amplifier is fabricated in a 0.25mum CMOS process. It has a measured 1-dB compression point between 1920MHz and 1980MHz of 21.3plusmn0.5dBm with a maximum PAE of 24%. The amplifier has sufficiently low ACLR for WCDMA (-33 dB) at an output power of 20 dBm