An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC
A 10-b 200-MSample/s digital-to-analog converter is optimized for low power and low area with plusmn25%, 0.1% incremental gain control. The converter uses a combined thermometer coded current-steering DAC and an R-2R load to achieve a compact layout and sub-muA LSB current. It provides more than 61d...
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| creator | Nejati, B. Larson, L. |
| description | A 10-b 200-MSample/s digital-to-analog converter is optimized for low power and low area with plusmn25%, 0.1% incremental gain control. The converter uses a combined thermometer coded current-steering DAC and an R-2R load to achieve a compact layout and sub-muA LSB current. It provides more than 61dB spurious-free dynamic range over 50MHz bandwidth within -20degC to +95degC temperature range and plusmn10% supply variation from a dual 2.5/1.8-V supply. The differential and integral non-linearity of the converter are within plusmn0.1LSB. The 0.55mm times 0.47mm converter is implemented in a 0.35/0.18-mum CMOS technology and the DAC core dissipates only 200muA static current from a 2.5V analog supply |
| doi_str_mv | 10.1109/CICC.2006.320870 |
| format | Conference Proceeding |
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The 0.55mm times 0.47mm converter is implemented in a 0.35/0.18-mum CMOS technology and the DAC core dissipates only 200muA static current from a 2.5V analog supply</description><identifier>ISSN: 0886-5930</identifier><identifier>ISBN: 1424400759</identifier><identifier>ISBN: 9781424400751</identifier><identifier>EISSN: 2152-3630</identifier><identifier>EISBN: 9781424400768</identifier><identifier>EISBN: 1424400767</identifier><identifier>DOI: 10.1109/CICC.2006.320870</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; CMOS digital integrated circuits ; CMOS technology ; Dynamic range ; Energy consumption ; Gain control ; Linearity ; Resistors ; Switches ; Wireless communication</subject><ispartof>IEEE Custom Integrated Circuits Conference 2006, 2006, p.161-164</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4114931$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4114931$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nejati, B.</creatorcontrib><creatorcontrib>Larson, L.</creatorcontrib><title>An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC</title><title>IEEE Custom Integrated Circuits Conference 2006</title><addtitle>CICC</addtitle><description>A 10-b 200-MSample/s digital-to-analog converter is optimized for low power and low area with plusmn25%, 0.1% incremental gain control. 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The 0.55mm times 0.47mm converter is implemented in a 0.35/0.18-mum CMOS technology and the DAC core dissipates only 200muA static current from a 2.5V analog supply</description><subject>Bandwidth</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS technology</subject><subject>Dynamic range</subject><subject>Energy consumption</subject><subject>Gain control</subject><subject>Linearity</subject><subject>Resistors</subject><subject>Switches</subject><subject>Wireless communication</subject><issn>0886-5930</issn><issn>2152-3630</issn><isbn>1424400759</isbn><isbn>9781424400751</isbn><isbn>9781424400768</isbn><isbn>1424400767</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1jctOwzAQRc1Loi3dI7HxDzid8YwdexmZV6VWWRTYVo7jSEEUVUk38G18A98E4rG6RzrSuUJcIhSI4BdhGUKhAWxBGlwJR2LuS4esmQFK647FRKPRiizBiZj-C-NPxQScs8p4gnMxHcdnAPTe6Ymw1aushhxlvT_0u_49t1IXRj1JBNXI7zO13izGH_j8qGRY1xt5XYULcdbFlzHP_3YmHm9vHsK9WtV3y1CtVI-lOagmpdgYbtHH7DjF2HbcRGMTRc-ZjW66RBk7yk4n8lazNmBbLCNbah3RTFz9dvuc83Y_9Ls4vG0ZkT0hfQG7aUUX</recordid><startdate>200609</startdate><enddate>200609</enddate><creator>Nejati, B.</creator><creator>Larson, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200609</creationdate><title>An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC</title><author>Nejati, B. ; Larson, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-bccab54d19ae84caadf4ba56c3a94e452bfc3e1f3e82c396242506d17a463d833</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Bandwidth</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS technology</topic><topic>Dynamic range</topic><topic>Energy consumption</topic><topic>Gain control</topic><topic>Linearity</topic><topic>Resistors</topic><topic>Switches</topic><topic>Wireless communication</topic><toplevel>online_resources</toplevel><creatorcontrib>Nejati, B.</creatorcontrib><creatorcontrib>Larson, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nejati, B.</au><au>Larson, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC</atitle><btitle>IEEE Custom Integrated Circuits Conference 2006</btitle><stitle>CICC</stitle><date>2006-09</date><risdate>2006</risdate><spage>161</spage><epage>164</epage><pages>161-164</pages><issn>0886-5930</issn><eissn>2152-3630</eissn><isbn>1424400759</isbn><isbn>9781424400751</isbn><eisbn>9781424400768</eisbn><eisbn>1424400767</eisbn><abstract>A 10-b 200-MSample/s digital-to-analog converter is optimized for low power and low area with plusmn25%, 0.1% incremental gain control. The converter uses a combined thermometer coded current-steering DAC and an R-2R load to achieve a compact layout and sub-muA LSB current. It provides more than 61dB spurious-free dynamic range over 50MHz bandwidth within -20degC to +95degC temperature range and plusmn10% supply variation from a dual 2.5/1.8-V supply. The differential and integral non-linearity of the converter are within plusmn0.1LSB. The 0.55mm times 0.47mm converter is implemented in a 0.35/0.18-mum CMOS technology and the DAC core dissipates only 200muA static current from a 2.5V analog supply</abstract><pub>IEEE</pub><doi>10.1109/CICC.2006.320870</doi><tpages>4</tpages></addata></record> |
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| issn | 0886-5930 2152-3630 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth CMOS digital integrated circuits CMOS technology Dynamic range Energy consumption Gain control Linearity Resistors Switches Wireless communication |
| title | An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC |
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