Open Source On-Chip Logic Analyzer for FPGA-s

In this paper, principles of an FPGA internal logic analyzer are presented. The analyzer code is written in VHDL and inserted into design at the source description level. This allows to keep it independent of used design software and FPGA architecture. This analyzer was created under GPL license so that everyone can use and modify it. First, the existing commercial tools are described in brief. Then the architecture of the created analyzer is described. It is shown that this kind of a logic analyzer is small enough to fit inside smaller modern FPGA-s and that it runs fast enough to be used in wide range of designs, Jn addition, possible improvements are described