Future trends in charge trapping memories
Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of n...
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| creator | Kuesters, K.-H. Ludwig, C. Mikolajick, T. Nagel, N. Specht, M. Pissors, V. Schulze, N. Stein, E. Willer, J. |
| description | Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques |
| doi_str_mv | 10.1109/ICSICT.2006.306473 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4098221</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4098221</ieee_id><sourcerecordid>4098221</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-dc8823e1ce4eda6ec16107801c23c8d749c3b7cc06f906fb09cc37b41bb788523</originalsourceid><addsrcrecordid>eNo1jkFLxDAUhCOyoO72D-ilVw-tL8lrkxyluGthwYO9L-3r2zVia0m6B_-9FXVgGL45DCPErYRcSnAPdfVaV02uAMpcQ4lGX4gbiQoRZCmLS5E4Y_8Z8EokMb7DIixQa3Mt7rfn-Rw4nQOPfUz9mNJbG04_RTtNfjylAw-fwXPciNWx_Yic_OVaNNunpnrO9i-7unrcZ97BnPVkrdIsiZH7tmRaboCxIElpsr1BR7ozRFAe3eIOHJE2HcquM9YWSq_F3e-sZ-bDFPzQhq8DgrNKSf0Nao1CHg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Future trends in charge trapping memories</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kuesters, K.-H. ; Ludwig, C. ; Mikolajick, T. ; Nagel, N. ; Specht, M. ; Pissors, V. ; Schulze, N. ; Stein, E. ; Willer, J.</creator><creatorcontrib>Kuesters, K.-H. ; Ludwig, C. ; Mikolajick, T. ; Nagel, N. ; Specht, M. ; Pissors, V. ; Schulze, N. ; Stein, E. ; Willer, J.</creatorcontrib><description>Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques</description><identifier>ISBN: 9781424401604</identifier><identifier>ISBN: 1424401607</identifier><identifier>EISBN: 1424401615</identifier><identifier>EISBN: 9781424401611</identifier><identifier>DOI: 10.1109/ICSICT.2006.306473</identifier><language>eng</language><subject>Costs ; Dielectric materials ; Electron traps ; Flash memory ; High K dielectric materials ; High-K gate dielectrics ; Nonvolatile memory ; Production ; SONOS devices ; Technological innovation</subject><ispartof>2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.740-743</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4098221$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4098221$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kuesters, K.-H.</creatorcontrib><creatorcontrib>Ludwig, C.</creatorcontrib><creatorcontrib>Mikolajick, T.</creatorcontrib><creatorcontrib>Nagel, N.</creatorcontrib><creatorcontrib>Specht, M.</creatorcontrib><creatorcontrib>Pissors, V.</creatorcontrib><creatorcontrib>Schulze, N.</creatorcontrib><creatorcontrib>Stein, E.</creatorcontrib><creatorcontrib>Willer, J.</creatorcontrib><title>Future trends in charge trapping memories</title><title>2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings</title><addtitle>ICSICT</addtitle><description>Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques</description><subject>Costs</subject><subject>Dielectric materials</subject><subject>Electron traps</subject><subject>Flash memory</subject><subject>High K dielectric materials</subject><subject>High-K gate dielectrics</subject><subject>Nonvolatile memory</subject><subject>Production</subject><subject>SONOS devices</subject><subject>Technological innovation</subject><isbn>9781424401604</isbn><isbn>1424401607</isbn><isbn>1424401615</isbn><isbn>9781424401611</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1jkFLxDAUhCOyoO72D-ilVw-tL8lrkxyluGthwYO9L-3r2zVia0m6B_-9FXVgGL45DCPErYRcSnAPdfVaV02uAMpcQ4lGX4gbiQoRZCmLS5E4Y_8Z8EokMb7DIixQa3Mt7rfn-Rw4nQOPfUz9mNJbG04_RTtNfjylAw-fwXPciNWx_Yic_OVaNNunpnrO9i-7unrcZ97BnPVkrdIsiZH7tmRaboCxIElpsr1BR7ozRFAe3eIOHJE2HcquM9YWSq_F3e-sZ-bDFPzQhq8DgrNKSf0Nao1CHg</recordid><startdate>200610</startdate><enddate>200610</enddate><creator>Kuesters, K.-H.</creator><creator>Ludwig, C.</creator><creator>Mikolajick, T.</creator><creator>Nagel, N.</creator><creator>Specht, M.</creator><creator>Pissors, V.</creator><creator>Schulze, N.</creator><creator>Stein, E.</creator><creator>Willer, J.</creator><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200610</creationdate><title>Future trends in charge trapping memories</title><author>Kuesters, K.-H. ; Ludwig, C. ; Mikolajick, T. ; Nagel, N. ; Specht, M. ; Pissors, V. ; Schulze, N. ; Stein, E. ; Willer, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-dc8823e1ce4eda6ec16107801c23c8d749c3b7cc06f906fb09cc37b41bb788523</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Costs</topic><topic>Dielectric materials</topic><topic>Electron traps</topic><topic>Flash memory</topic><topic>High K dielectric materials</topic><topic>High-K gate dielectrics</topic><topic>Nonvolatile memory</topic><topic>Production</topic><topic>SONOS devices</topic><topic>Technological innovation</topic><toplevel>online_resources</toplevel><creatorcontrib>Kuesters, K.-H.</creatorcontrib><creatorcontrib>Ludwig, C.</creatorcontrib><creatorcontrib>Mikolajick, T.</creatorcontrib><creatorcontrib>Nagel, N.</creatorcontrib><creatorcontrib>Specht, M.</creatorcontrib><creatorcontrib>Pissors, V.</creatorcontrib><creatorcontrib>Schulze, N.</creatorcontrib><creatorcontrib>Stein, E.</creatorcontrib><creatorcontrib>Willer, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuesters, K.-H.</au><au>Ludwig, C.</au><au>Mikolajick, T.</au><au>Nagel, N.</au><au>Specht, M.</au><au>Pissors, V.</au><au>Schulze, N.</au><au>Stein, E.</au><au>Willer, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Future trends in charge trapping memories</atitle><btitle>2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings</btitle><stitle>ICSICT</stitle><date>2006-10</date><risdate>2006</risdate><spage>740</spage><epage>743</epage><pages>740-743</pages><isbn>9781424401604</isbn><isbn>1424401607</isbn><eisbn>1424401615</eisbn><eisbn>9781424401611</eisbn><abstract>Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g. including Fin-Fets. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques</abstract><doi>10.1109/ICSICT.2006.306473</doi><tpages>4</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Costs Dielectric materials Electron traps Flash memory High K dielectric materials High-K gate dielectrics Nonvolatile memory Production SONOS devices Technological innovation |
| title | Future trends in charge trapping memories |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T16%3A09%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Future%20trends%20in%20charge%20trapping%20memories&rft.btitle=2006%208th%20International%20Conference%20on%20Solid-State%20and%20Integrated%20Circuit%20Technology%20Proceedings&rft.au=Kuesters,%20K.-H.&rft.date=2006-10&rft.spage=740&rft.epage=743&rft.pages=740-743&rft.isbn=9781424401604&rft.isbn_list=1424401607&rft_id=info:doi/10.1109/ICSICT.2006.306473&rft_dat=%3Cieee_6IE%3E4098221%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424401615&rft.eisbn_list=9781424401611&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4098221&rfr_iscdi=true |