Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks

Many modern designs have transient and localized failures which can be attributed to excessive instantaneous power consumption known as di/dt or IR drop. IR drop is problematic because power rails may not be sized correctly for the load they must handle in both function and test, and so there might be localized "hot spots". The current technique for mitigating this issue is at design time, when the power rails are analyzed using tools attempting to predict the actual current spikes and limiting their effect on device performance. This paper describes a methodology using on-chip process monitoring circuits to help identify and localize IR drop "hot spots". This methodology utilizes a circuit that is easy to integrate on chip and use in a production environment. Furthermore, a comparison between the predicted IR drop and the actual was presented