A Mimo Receiver SOC for CDMA Applications

In this paper, we present a systems-on-chip (SoC) design for the 3G code division multiple access (CDMA) receiver using the multiple-input multiple-output (MIMO) technique. Our chip integrates the entire digital signal processing part of the receiver. Furthermore, the proposed design can be reconfigured in real-time to handle different modulation schemes based on the signal-to-noise ratio, resulting in the highly efficient use of spectrum and energy. Designed using a 0.18 mum standard cell library, our chip has a core area of 20 mm 2 and achieves a maximal throughput of 5 Mbps in simulation with 610 mW power dissipation.