Reducing Charge Injection in Active-Matrix a-Si TFT Pixels
A technique for reducing charge injection in active-matrix amorphous silicon thin film transistor pixels is presented. Using a gate pulse with two falling rates, more than 50% reduction in the induced error voltage was achieved
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creator | Ashtiani, S.J. Nathan, A. |
description | A technique for reducing charge injection in active-matrix amorphous silicon thin film transistor pixels is presented. Using a gate pulse with two falling rates, more than 50% reduction in the induced error voltage was achieved |
doi_str_mv | 10.1109/LEOS.2006.279204 |
format | Conference Proceeding |
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Using a gate pulse with two falling rates, more than 50% reduction in the induced error voltage was achieved</abstract><pub>IEEE</pub><doi>10.1109/LEOS.2006.279204</doi><tpages>2</tpages></addata></record> |
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ispartof | LEOS 2006 - 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2006, p.440-441 |
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language | eng |
recordid | cdi_ieee_primary_4054246 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Active matrix liquid crystal displays Active matrix organic light emitting diodes Active matrix technology Amorphous silicon Backplanes Circuits Liquid crystal displays Switches Thin film transistors Voltage |
title | Reducing Charge Injection in Active-Matrix a-Si TFT Pixels |
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