Tapered buffers for gate array and standard cell circuits

Tapered buffer systems are often used in CMOS circuits to drive large capacitive loads. Well accepted tapered buffer design practices neglect the effects of local interconnect capacitance between the buffer stages. However in many design methodologies, particularly semi-custom ASICs based on gate array or standard cell circuits, buffer stages may not be physically abutted, and therefore significant stage-to-stage local interconnect capacitance may exist. This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C/sup 3/RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore the propagation delay of each buffer stage also remains constant. Significant reductions in power dissipation and active area, as well as reduced propagation delay, are exhibited as compared with tapered buffers which neglect local interconnect capacitance.< >