DFT of the Cell Processor and its Impact on EDA Test Softwar
This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processo...
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| creator | Bushard, L. Chelstrom, N. Ferguson, S. Keller, B. |
| description | This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock |
| doi_str_mv | 10.1109/ATS.2006.260957 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4030793</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4030793</ieee_id><sourcerecordid>4030793</sourcerecordid><originalsourceid>FETCH-LOGICAL-i862-575af99b8b350b74446c2208321265c6ff882a948ce2048c4820de2719e80eff3</originalsourceid><addsrcrecordid>eNotj8tqwzAQAEUfUDfNuYde9AN2VytLWkEvJo82EGghvgfZWVEXJw6WofTvG2gvM7eBEeJRQaEU-Oeq3hUIYAu04I27Ehlq53KjyV6LuXcEznqDFsndiEwBqdw5be7EfUpfAKDB60y8LNe1HKKcPlkuuO_lxzi0nNIwynA6yG5KcnM8h3aSw0mulpWsOU1yN8TpO4wP4jaGPvH83zNRr1f14i3fvr9uFtU278hibpwJ0fuGGm2gcWVZ2hYRSKNCa1obIxEGX1LLCBeWhHBgdMozAceoZ-LpL9sx8_48dscw_uzLy4HzWv8COPhGNg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>DFT of the Cell Processor and its Impact on EDA Test Softwar</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bushard, L. ; Chelstrom, N. ; Ferguson, S. ; Keller, B.</creator><creatorcontrib>Bushard, L. ; Chelstrom, N. ; Ferguson, S. ; Keller, B.</creatorcontrib><description>This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock</description><identifier>ISSN: 1081-7735</identifier><identifier>ISBN: 9780769526287</identifier><identifier>ISBN: 0769526284</identifier><identifier>EISSN: 2377-5386</identifier><identifier>DOI: 10.1109/ATS.2006.260957</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Built-in self-test ; Clocks ; Electronic design automation and methodology ; Frequency ; Logic ; Microwave integrated circuits ; Pipelines ; Random access memory ; Software testing</subject><ispartof>2006 15th Asian Test Symposium, 2006, p.369-374</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4030793$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4030793$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bushard, L.</creatorcontrib><creatorcontrib>Chelstrom, N.</creatorcontrib><creatorcontrib>Ferguson, S.</creatorcontrib><creatorcontrib>Keller, B.</creatorcontrib><title>DFT of the Cell Processor and its Impact on EDA Test Softwar</title><title>2006 15th Asian Test Symposium</title><addtitle>ATS</addtitle><description>This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock</description><subject>Automatic test pattern generation</subject><subject>Built-in self-test</subject><subject>Clocks</subject><subject>Electronic design automation and methodology</subject><subject>Frequency</subject><subject>Logic</subject><subject>Microwave integrated circuits</subject><subject>Pipelines</subject><subject>Random access memory</subject><subject>Software testing</subject><issn>1081-7735</issn><issn>2377-5386</issn><isbn>9780769526287</isbn><isbn>0769526284</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tqwzAQAEUfUDfNuYde9AN2VytLWkEvJo82EGghvgfZWVEXJw6WofTvG2gvM7eBEeJRQaEU-Oeq3hUIYAu04I27Ehlq53KjyV6LuXcEznqDFsndiEwBqdw5be7EfUpfAKDB60y8LNe1HKKcPlkuuO_lxzi0nNIwynA6yG5KcnM8h3aSw0mulpWsOU1yN8TpO4wP4jaGPvH83zNRr1f14i3fvr9uFtU278hibpwJ0fuGGm2gcWVZ2hYRSKNCa1obIxEGX1LLCBeWhHBgdMozAceoZ-LpL9sx8_48dscw_uzLy4HzWv8COPhGNg</recordid><startdate>200611</startdate><enddate>200611</enddate><creator>Bushard, L.</creator><creator>Chelstrom, N.</creator><creator>Ferguson, S.</creator><creator>Keller, B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200611</creationdate><title>DFT of the Cell Processor and its Impact on EDA Test Softwar</title><author>Bushard, L. ; Chelstrom, N. ; Ferguson, S. ; Keller, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i862-575af99b8b350b74446c2208321265c6ff882a948ce2048c4820de2719e80eff3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2006</creationdate><topic>Automatic test pattern generation</topic><topic>Built-in self-test</topic><topic>Clocks</topic><topic>Electronic design automation and methodology</topic><topic>Frequency</topic><topic>Logic</topic><topic>Microwave integrated circuits</topic><topic>Pipelines</topic><topic>Random access memory</topic><topic>Software testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Bushard, L.</creatorcontrib><creatorcontrib>Chelstrom, N.</creatorcontrib><creatorcontrib>Ferguson, S.</creatorcontrib><creatorcontrib>Keller, B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bushard, L.</au><au>Chelstrom, N.</au><au>Ferguson, S.</au><au>Keller, B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>DFT of the Cell Processor and its Impact on EDA Test Softwar</atitle><btitle>2006 15th Asian Test Symposium</btitle><stitle>ATS</stitle><date>2006-11</date><risdate>2006</risdate><spage>369</spage><epage>374</epage><pages>369-374</pages><issn>1081-7735</issn><eissn>2377-5386</eissn><isbn>9780769526287</isbn><isbn>0769526284</isbn><abstract>This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock</abstract><pub>IEEE</pub><doi>10.1109/ATS.2006.260957</doi><tpages>6</tpages></addata></record> |
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| ispartof | 2006 15th Asian Test Symposium, 2006, p.369-374 |
| issn | 1081-7735 2377-5386 |
| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic test pattern generation Built-in self-test Clocks Electronic design automation and methodology Frequency Logic Microwave integrated circuits Pipelines Random access memory Software testing |
| title | DFT of the Cell Processor and its Impact on EDA Test Softwar |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T15%3A19%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=DFT%20of%20the%20Cell%20Processor%20and%20its%20Impact%20on%20EDA%20Test%20Softwar&rft.btitle=2006%2015th%20Asian%20Test%20Symposium&rft.au=Bushard,%20L.&rft.date=2006-11&rft.spage=369&rft.epage=374&rft.pages=369-374&rft.issn=1081-7735&rft.eissn=2377-5386&rft.isbn=9780769526287&rft.isbn_list=0769526284&rft_id=info:doi/10.1109/ATS.2006.260957&rft_dat=%3Cieee_6IE%3E4030793%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4030793&rfr_iscdi=true |