DFT of the Cell Processor and its Impact on EDA Test Softwar

DFT of the Cell Processor and its Impact on EDA Test Softwar

This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processo...

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Bibliographische Detailangaben
Hauptverfasser: Bushard, L., Chelstrom, N., Ferguson, S., Keller, B.
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Automatic test pattern generation
Built-in self-test
Clocks
Electronic design automation and methodology
Frequency
Logic
Microwave integrated circuits
Pipelines
Random access memory
Software testing
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Beschreibung
Zusammenfassung:This paper describes aspects of the Cell processor DFT and its effects on the EDA software used to process it. The Cell processor is a very complex multi-core design, and the use of high frequency clocks near 4 GHz drove DFT decisions that had significant implications on several levels. The processor had to support Logic BIST, Memory BIST, OPMSR+, SerDes I/O-WRAP as well as traditional scan-based ATPG all using a free-running high-speed clock
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2006.260957