A Comparison between 63nm 8Gb and 90nm 4Gb Multi-Level Cell NAND Flash Memory for Mass Storage Application

This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise