Efficient scalable architectures for Viterbi decoders

Viterbi decoders (VDs) are widely used today for the decoding of convolutional codes in forward error correction schemes. Efficient deeply pipelined VLSI architectures, the generalized cascade VD and the trellis pipeline-interleaving (TPI) VD are adaptable to a given data rate only to a limited exte...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bitterlich, S., Meyr, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Convolutional codes Dynamic programming Equations Forward error correction Hardware Maximum likelihood decoding Throughput Very large scale integration Viterbi algorithm
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