Efficient scalable architectures for Viterbi decoders

Viterbi decoders (VDs) are widely used today for the decoding of convolutional codes in forward error correction schemes. Efficient deeply pipelined VLSI architectures, the generalized cascade VD and the trellis pipeline-interleaving (TPI) VD are adaptable to a given data rate only to a limited extent. The authors propose a novel unified class of deeply pipelined architectures, the scalable parallel Viterbi decoders (SPVD) that allows for a smoother adaptation to a given data rate. Therefore, the designer is able to choose an architecture that nearly exactly fulfills the throughput demands of the application without wasting silicon area by using a badly adapted architecture. This class of SPVDs contains the GCVD, TPI, node-serial and node-parallel architectures as important subclasses. Thus, it provides a framework for a unified description of the existing architectures as well. Furthermore, architectures can be derived that allow for 100% utilization making the complicated rate synchronization superfluous or trivial.< >