Layout compaction with minimized delay bound on timing critical paths

A layout compaction problem which aims at both performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed in order to reduce the execution time.< >