KaGen-A generator of static CMOS-cell layout from circuit schematics
KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1848 vol.3 |
|---|---|
| container_issue | |
| container_start_page | 1845 |
| container_title | |
| container_volume | |
| creator | Doerffer, K. Teby, A.T. Anton, O. Mlynski, D.A. |
| description | KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< > |
| doi_str_mv | 10.1109/ISCAS.1993.394106 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_394106</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>394106</ieee_id><sourcerecordid>394106</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-e6dfa22688f0b31fb0f0afc233ab95ba80e1e8ed627ebd64cf6c90fa49461d4b3</originalsourceid><addsrcrecordid>eNotj11LwzAYhQMiKLM_QK_yB1rffCxNLkvVOZzsorsfSfpGK-0qSXaxf-9kOxx4bg4PHEIeGVSMgXled23TVcwYUQkjGagbUphaw7mCcc3kHSlS-oFz5BIMh3vy8mFXeCgb-oUHjDbPkc6Bpmzz4Gn7ue1Kj-NIR3uaj5mGOE_UD9Efh0yT_8bpf5ceyG2wY8LiygXZvb3u2vdys12t22ZTDrrOJao-WM6V1gGcYMFBABs8F8I6s3RWAzLU2Cteo-uV9EF5A8FKIxXrpRML8nTRDoi4_43DZONpf3kq_gAcykm-</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>KaGen-A generator of static CMOS-cell layout from circuit schematics</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Doerffer, K. ; Teby, A.T. ; Anton, O. ; Mlynski, D.A.</creator><creatorcontrib>Doerffer, K. ; Teby, A.T. ; Anton, O. ; Mlynski, D.A.</creatorcontrib><description>KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< ></description><identifier>ISBN: 9780780312814</identifier><identifier>ISBN: 0780312813</identifier><identifier>DOI: 10.1109/ISCAS.1993.394106</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; CMOS logic circuits ; Collision mitigation ; Digital signal processing ; Minimization methods ; Neodymium ; Partitioning algorithms ; Strips ; Variable structure systems</subject><ispartof>1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993, p.1845-1848 vol.3</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/394106$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/394106$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Doerffer, K.</creatorcontrib><creatorcontrib>Teby, A.T.</creatorcontrib><creatorcontrib>Anton, O.</creatorcontrib><creatorcontrib>Mlynski, D.A.</creatorcontrib><title>KaGen-A generator of static CMOS-cell layout from circuit schematics</title><title>1993 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< ></description><subject>Algorithm design and analysis</subject><subject>CMOS logic circuits</subject><subject>Collision mitigation</subject><subject>Digital signal processing</subject><subject>Minimization methods</subject><subject>Neodymium</subject><subject>Partitioning algorithms</subject><subject>Strips</subject><subject>Variable structure systems</subject><isbn>9780780312814</isbn><isbn>0780312813</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1993</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj11LwzAYhQMiKLM_QK_yB1rffCxNLkvVOZzsorsfSfpGK-0qSXaxf-9kOxx4bg4PHEIeGVSMgXled23TVcwYUQkjGagbUphaw7mCcc3kHSlS-oFz5BIMh3vy8mFXeCgb-oUHjDbPkc6Bpmzz4Gn7ue1Kj-NIR3uaj5mGOE_UD9Efh0yT_8bpf5ceyG2wY8LiygXZvb3u2vdys12t22ZTDrrOJao-WM6V1gGcYMFBABs8F8I6s3RWAzLU2Cteo-uV9EF5A8FKIxXrpRML8nTRDoi4_43DZONpf3kq_gAcykm-</recordid><startdate>199305</startdate><enddate>199305</enddate><creator>Doerffer, K.</creator><creator>Teby, A.T.</creator><creator>Anton, O.</creator><creator>Mlynski, D.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199305</creationdate><title>KaGen-A generator of static CMOS-cell layout from circuit schematics</title><author>Doerffer, K. ; Teby, A.T. ; Anton, O. ; Mlynski, D.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-e6dfa22688f0b31fb0f0afc233ab95ba80e1e8ed627ebd64cf6c90fa49461d4b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Algorithm design and analysis</topic><topic>CMOS logic circuits</topic><topic>Collision mitigation</topic><topic>Digital signal processing</topic><topic>Minimization methods</topic><topic>Neodymium</topic><topic>Partitioning algorithms</topic><topic>Strips</topic><topic>Variable structure systems</topic><toplevel>online_resources</toplevel><creatorcontrib>Doerffer, K.</creatorcontrib><creatorcontrib>Teby, A.T.</creatorcontrib><creatorcontrib>Anton, O.</creatorcontrib><creatorcontrib>Mlynski, D.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Doerffer, K.</au><au>Teby, A.T.</au><au>Anton, O.</au><au>Mlynski, D.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>KaGen-A generator of static CMOS-cell layout from circuit schematics</atitle><btitle>1993 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1993-05</date><risdate>1993</risdate><spage>1845</spage><epage>1848 vol.3</epage><pages>1845-1848 vol.3</pages><isbn>9780780312814</isbn><isbn>0780312813</isbn><abstract>KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< ></abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1993.394106</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9780780312814 |
| ispartof | 1993 IEEE International Symposium on Circuits and Systems (ISCAS), 1993, p.1845-1848 vol.3 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_394106 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis CMOS logic circuits Collision mitigation Digital signal processing Minimization methods Neodymium Partitioning algorithms Strips Variable structure systems |
| title | KaGen-A generator of static CMOS-cell layout from circuit schematics |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T15%3A24%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=KaGen-A%20generator%20of%20static%20CMOS-cell%20layout%20from%20circuit%20schematics&rft.btitle=1993%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Doerffer,%20K.&rft.date=1993-05&rft.spage=1845&rft.epage=1848%20vol.3&rft.pages=1845-1848%20vol.3&rft.isbn=9780780312814&rft.isbn_list=0780312813&rft_id=info:doi/10.1109/ISCAS.1993.394106&rft_dat=%3Cieee_6IE%3E394106%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=394106&rfr_iscdi=true |