KaGen-A generator of static CMOS-cell layout from circuit schematics

KaGen-A generator of static CMOS-cell layout from circuit schematics

KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Doerffer, K., Teby, A.T., Anton, O., Mlynski, D.A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Algorithm design and analysis
CMOS logic circuits
Collision mitigation
Digital signal processing
Minimization methods
Neodymium
Partitioning algorithms
Strips
Variable structure systems
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Beschreibung
Zusammenfassung:KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< >
DOI:10.1109/ISCAS.1993.394106