Bounds for distributed parameter trees

Bounds for distributed parameter trees

The interconnection wires in VLSI circuits are modelled by telegraph equations. Upper and lower bounds are given for node voltages of a tree network composed of such wires and ended in lumped capacitors. These bounds are easily computable from circuit parameters and are sufficiently tight to be used...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Marinov, C.A., Neittaanmaki, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitors
Delay
Differential equations
Integrated circuit interconnections
Mathematical model
Mathematics
Telegraphy
Very large scale integration
Voltage
Wires
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Beschreibung
Zusammenfassung:The interconnection wires in VLSI circuits are modelled by telegraph equations. Upper and lower bounds are given for node voltages of a tree network composed of such wires and ended in lumped capacitors. These bounds are easily computable from circuit parameters and are sufficiently tight to be used in initial design stages of digital circuits.< >
DOI:10.1109/ISCAS.1993.394032