A 3/5 V compatible I/O buffer

A 3/5 V compatible I/O buffer

The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals. The design has been processed in 0.8- and 0.6-/spl mu/m CMOS processes. A comparison of results is presented.< >

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Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 1995-07, Vol.30 (7), p.823-825
Hauptverfasser: Pelgrom, M.J.M., Dijkmans, E.C.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Bonding
Circuit properties
CMOS process
Digital circuits
Digital integrated circuits
Diodes
Driver circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Power supplies
Signal design
Stress
Switches
Voltage
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Beschreibung
Zusammenfassung:The design of a digital input/output buffer is described for operation in 3.3-V IC's with 5-V input signals. The design has been processed in 0.8- and 0.6-/spl mu/m CMOS processes. A comparison of results is presented.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.391124