Implementation of systolic multipliers and digital filters via signal flow-graph transformations

Implementation of systolic multipliers and digital filters via signal flow-graph transformations

Massive insertion of delay elements in a one-way signal flow-graph of an FIR digital filter, and/or proper transfer of delay elements between edges in a two-way signal flow-graph lead to systolic arrays for the implementation of a serial-parallel multiplier, a bit-parallel multiplier, and an FIR dig...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Pekmestzi, K.Z., Caraiscos, C.G.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Delay
Digital filters
Finite impulse response filter
Interleaved codes
Merging
Pipelines
Systolic arrays
Throughput
Transfer functions
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Massive insertion of delay elements in a one-way signal flow-graph of an FIR digital filter, and/or proper transfer of delay elements between edges in a two-way signal flow-graph lead to systolic arrays for the implementation of a serial-parallel multiplier, a bit-parallel multiplier, and an FIR digital filter. All of them are of the merged type and exhibit lower latency than existing ones, without any increase in throughput or circuitry.< >
DOI:10.1109/MELCON.1994.381133