A VLSI architecture for fast inversion in GF(2/sup m/)
A new algorithm for performing fast inversion in GF (2/sup m/) is presented. The algorithm requires O(mlog/sub 2/ m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation.< >
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Veröffentlicht in: | IEEE transactions on computers 1989-10, Vol.38 (10), p.1383-1386 |
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container_title | IEEE transactions on computers |
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creator | Feng, G.-L. |
description | A new algorithm for performing fast inversion in GF (2/sup m/) is presented. The algorithm requires O(mlog/sub 2/ m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation.< > |
doi_str_mv | 10.1109/12.35833 |
format | Article |
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The algorithm requires O(mlog/sub 2/ m) computation time. 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The algorithm requires O(mlog/sub 2/ m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation.< ></description><subject>Algorithm design and analysis</subject><subject>Applied sciences</subject><subject>Coding, codes</subject><subject>Computer architecture</subject><subject>Cryptography</subject><subject>Decoding</subject><subject>Error correction codes</subject><subject>Exact sciences and technology</subject><subject>Galois fields</subject><subject>Information, signal and communications theory</subject><subject>Pipelines</subject><subject>Reed-Solomon codes</subject><subject>Signal and communications theory</subject><subject>Signal processing algorithms</subject><subject>Telecommunications and information theory</subject><subject>Very large scale integration</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1989</creationdate><recordtype>article</recordtype><recordid>eNo9j81Lw0AUxBdRMFbBq7c9eKiHNG93k_04lmJrIeDBj2vYbN5ipE3Dbir43xuN9DSPmR_DG0JuGSwYA5MxvhCFFuKMJKwoVGpMIc9JAsB0akQOl-Qqxk8AkBxMQuSSvpcvW2qD-2gHdMMxIPWHQL2NA227LwyxPXTjRTfrOc_isaf77OGaXHi7i3jzrzPytn58XT2l5fNmu1qWqeOKD6kAUwidA_NO8cIgzzUq1QhtweQGfQ3N6HOLda69G_-unc2VR4dYW93UYkbmU68LhxgD-qoP7d6G74pB9bu3Yrz62zui9xPa2-jszgfbuTaeeClBg5QjdjdhLSKe0qniB8aVWkU</recordid><startdate>19891001</startdate><enddate>19891001</enddate><creator>Feng, G.-L.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19891001</creationdate><title>A VLSI architecture for fast inversion in GF(2/sup m/)</title><author>Feng, G.-L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c272t-309538401fc7259e248e77d38a0949efb0d7252aeb48fc358bca47feceeba8db3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1989</creationdate><topic>Algorithm design and analysis</topic><topic>Applied sciences</topic><topic>Coding, codes</topic><topic>Computer architecture</topic><topic>Cryptography</topic><topic>Decoding</topic><topic>Error correction codes</topic><topic>Exact sciences and technology</topic><topic>Galois fields</topic><topic>Information, signal and communications theory</topic><topic>Pipelines</topic><topic>Reed-Solomon codes</topic><topic>Signal and communications theory</topic><topic>Signal processing algorithms</topic><topic>Telecommunications and information theory</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Feng, G.-L.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Feng, G.-L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A VLSI architecture for fast inversion in GF(2/sup m/)</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>1989-10-01</date><risdate>1989</risdate><volume>38</volume><issue>10</issue><spage>1383</spage><epage>1386</epage><pages>1383-1386</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>A new algorithm for performing fast inversion in GF (2/sup m/) is presented. The algorithm requires O(mlog/sub 2/ m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/12.35833</doi><tpages>4</tpages></addata></record> |
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subjects | Algorithm design and analysis Applied sciences Coding, codes Computer architecture Cryptography Decoding Error correction codes Exact sciences and technology Galois fields Information, signal and communications theory Pipelines Reed-Solomon codes Signal and communications theory Signal processing algorithms Telecommunications and information theory Very large scale integration |
title | A VLSI architecture for fast inversion in GF(2/sup m/) |
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