A CMOS RISC CPU with on-chip parallel cache

A CMOS RISC CPU with on-chip parallel cache

This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz)...

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Hauptverfasser: Rashid, E., Delano, E., Chan, K., Buckley, M., Zheng, J., Schumacher, F., Kurpanek, G., Shelton, J., Alexander, T., Noordeen, N., Ludwig, M., Scherer, A., Amir, C., Cheung, D., Sabada, P., Rajamani, R., Fiduccia, N., Ches, B., Eshghi, K., Eatock, F., Renfrow, D., Keller, J., Ilgenfritz, P., Krashinsky, I., Weatherspoon, D., Ranade, S., Goldberg, D., Bryg, W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CADCAM
Circuits
CMOS process
Computer aided manufacturing
Pipelines
Prefetching
Rails
Read-write memory
Reduced instruction set computing
Timing
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Beschreibung
Zusammenfassung:This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given.< >
DOI:10.1109/ISSCC.1994.344666