Reducing power dissipation in serially connected MOSFET circuits via transistor reordering

Reducing power dissipation in serially connected MOSFET circuits via transistor reordering

In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results...

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Bibliographische Detailangaben
Hauptverfasser: Hossain, R., Zheng, M., Albicki, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Capacitance
Circuit simulation
CMOS technology
MOSFET circuits
Power dissipation
Power measurement
Power MOSFET
Semiconductor device modeling
Very large scale integration
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Beschreibung
Zusammenfassung:In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates.< >
DOI:10.1109/ICCD.1994.331989