Exploring the limits of cycle time for VLSI processing

Exploring the limits of cycle time for VLSI processing

Theoretical cycle time of 17.5 hours has been demonstrated on 13-mask 0.35-/spl mu/m CMOS using 100% single-wafer processing and real-time process control. The process time during which "the wafer state was being altered" was only 9.4 hours. In this experiment, total cycle time of less tha...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Doering, R.R., Reed, D.W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
CMOS process
Electric breakdown
Instruments
Manufacturing processes
Metrology
Process control
Production facilities
Pulp manufacturing
Very large scale integration
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Zusammenfassung:Theoretical cycle time of 17.5 hours has been demonstrated on 13-mask 0.35-/spl mu/m CMOS using 100% single-wafer processing and real-time process control. The process time during which "the wafer state was being altered" was only 9.4 hours. In this experiment, total cycle time of less than 72 hours (3 days) was demonstrated. Under ideal conditions (e.g., no queues) it should be possible to manufacture advanced ICs with cycle times as short as approximately 2 hours per mask level.< >
DOI:10.1109/VLSIT.1994.324392