Design for reliability, testability and manufacturability of memory chips

The number of transistors on integrated-circuit chips is growing exponentially. This makes it increasingly difficult to satisfy the continuing demand for ever higher reliability of chips. The tools available to the chip architects and circuit designers for solving this predicament are discussed. The solutions include correct circuit placement and chip segmentation; logic and timing interlocks; low internal chip noise; optimized performance; circuits designed for ease of testability and for detectability of all defects; reduced sensitivity to manufacturing defects with relaxed layouts; wear-out mechanisms minimized by design; and low power consumption for reduced operating junction temperatures. These solutions and the design practices described have been implemented on 16-Mb and 18-Mb DRAM (dynamic random access memory) chips, each having more than 20 million transistors.< >