A novel high-speed silicon bipolar transistor utilizing SEG and CLSEG

The concept and fabrication results are presented for a novel high-speed silicon bipolar transistor structure using selective epitaxy (SEG) and confined lateral growth (CLSEG) to form a double self-aligned single crystal contacted device. It provides significant improvements in the parasitics C/sub...

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Veröffentlicht in:	IEEE transactions on electron devices 1994-05, Vol.41 (5), p.862-864
Hauptverfasser:	Siekkinen, J.W., Neudeck, G.W., Glenn, J.L., Venkatesan, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bipolar transistors Circuits Delay Electronics Epitaxial growth Etching Exact sciences and technology Fabrication Geometry Implants Parasitic capacitance Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Transistors
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Beschreibung
Zusammenfassung:	The concept and fabrication results are presented for a novel high-speed silicon bipolar transistor structure using selective epitaxy (SEG) and confined lateral growth (CLSEG) to form a double self-aligned single crystal contacted device. It provides significant improvements in the parasitics C/sub cb/ and C/sub cs/, and in the ECL gate delay.< >
ISSN:	0018-9383 1557-9646
DOI:	10.1109/16.285047