Gate dielectric integrity and reliability in 0.5- mu m CMOS technology

Gate dielectric process and process-integration decisions involving the 0.5- mu m 16-Mb DRAM process for 200-mm wafers are discussed. Process-integration issues before, during, and after thin gate dielectric growth all affect the resulting dielectric reliability. Processes which are critical factors...

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Bibliographische Detailangaben

Hauptverfasser:	Strong, A.W., Stamper, A.K., Bolam, R.J., Furukawa, T., Gow, C.J., Gow, T.R., Martin, D.W., Mittl, S.W., Nakos, J.S., Pennington, S.L.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Acceleration Capacitors CMOS technology Dielectrics Failure analysis Random access memory Stress Temperature Testing Voltage
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