Gate dielectric integrity and reliability in 0.5- mu m CMOS technology

Gate dielectric process and process-integration decisions involving the 0.5- mu m 16-Mb DRAM process for 200-mm wafers are discussed. Process-integration issues before, during, and after thin gate dielectric growth all affect the resulting dielectric reliability. Processes which are critical factors in gate dielectric integrity and reliability are discussed. IBM's 16-Mb DRAM CMOS technology employs shallow-trench isolation between the deep-trench storage capacitors. P-channel transfer devices are used and are connected to the deep-trench capacitors via a doped polysilicon surface strap. The gate dielectric is a 13-nm planar oxide and the transfer device channel lengths are 0.5 mu m. Gate dielectric yields were measured using long serpentine antenna test structures consisting of 128-kb cells in addition to segments of 16-Mb arrays. Dramatic gate dielectric reliability improvements have been achieved even with a starting point that was known to be less than optimal for the gate dielectric reliability. These improvements are graphically summarized.< >