On testability of differential split-level CMOS circuits

Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Aziz, S.M., Waller, W.A.J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit faults Circuit testing CMOS logic circuits CMOS technology DSL Electrical fault detection Fault detection Logic circuits Logic testing Monitoring
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