A 30 ns 256 Mb DRAM with multi-divided array structure

A 30 ns 256 Mb DRAM with multi-divided array structure

A 256-Mb DRAM (dynamic random-access memory) fabricated using 0.25- mu m CMOS technology is described. The DRAM has 16-b I/Os, 30-ns access time, and 35-mA operating current for 60-ns cycle time. Key circuits include a partial cell array activation scheme in a multidivided array structure with a dua...

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Hauptverfasser: Sugibayashi, T., Takeshima, T., Naritake, I., Matano, T., Takada, H., Aimoto, Y., Furuta, K., Fujita, M., Saeki, T., Sugawara, H., Murotani, T., Kasai, N., Shibahara, K., Nakajima, K., Hada, H., Hamada, T., Aizaki, N., Kunio, T., Kakehashi, E., Masumori, K., Tanigawa, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Artificial intelligence
Decoding
Driver circuits
High power amplifiers
National electric code
Power supplies
Random access memory
Synthetic aperture sonar
Time sharing computer systems
Voltage
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Zusammenfassung:A 256-Mb DRAM (dynamic random-access memory) fabricated using 0.25- mu m CMOS technology is described. The DRAM has 16-b I/Os, 30-ns access time, and 35-mA operating current for 60-ns cycle time. Key circuits include a partial cell array activation scheme in a multidivided array structure with a dual word-line format for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O (input/output) width and to reduce current, and a time-sharing refresh to maintain a conventional refresh period without increasing power-line voltage bounce.< >
DOI:10.1109/ISSCC.1993.280088