On-die parasitic effects and their impact on high-speed bipolar IC design

On-die parasitics can impose a significant barrier in the push to achieve higher speeds and integrate more functions. The various parasitics of devices and interconnects and their impact on circuit performance are reviewed. Within a given technology, there are a number of steps that can be taken to minimize the effects of parasitics and thereby maximize fast signal performance. These steps involve the approximate layout and sizing of individual devices, as well as floorplanning and routing of the functional blocks. Circuit design also plays a critical role in this context. The selection of circuit topology, physical partitioning, component values, and operating bias and signal levels has a large impact on high frequency performance. The author highlights some of these important considerations in high-speed IC design and layout.< >