A low-voltage metal-programmable SRAM compiler for gate array

A low-voltage metal-programmable SRAM compiler for gate array

A faster and more area efficient metal-programmable SRAM compiler for a 3.3 V 0.65 mu m effective CMOS sea-of-gates (SOG) array has been designed. A base cell, optimized for memory, features reduced bit and word-line parasitics in order to improve speed and provide high density SRAMs for ASIC applic...

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Bibliographische Detailangaben
Hauptverfasser: Svejda, F.J., Tupuri, R.S., Madhuri, S., Rath, R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application specific integrated circuits
Clocks
Costs
Design optimization
Instruments
Latches
Logic arrays
Parasitic capacitance
Personal digital assistants
Random access memory
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Zusammenfassung:A faster and more area efficient metal-programmable SRAM compiler for a 3.3 V 0.65 mu m effective CMOS sea-of-gates (SOG) array has been designed. A base cell, optimized for memory, features reduced bit and word-line parasitics in order to improve speed and provide high density SRAMs for ASIC applications.< >
DOI:10.1109/ASIC.1992.270210