A VLSI-chip for a hardware-accelerator for the simplex-method

A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employin...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Schutz, B., Klindworth, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Computer science Data structures Floating-point arithmetic Hardware Linear programming Mathematical model Numerical stability Read-write memory Roundoff errors
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