A VLSI-chip for a hardware-accelerator for the simplex-method

A VLSI-chip for a hardware-accelerator for the simplex-method

A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employin...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Schutz, B., Klindworth, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer architecture
Computer science
Data structures
Floating-point arithmetic
Hardware
Linear programming
Mathematical model
Numerical stability
Read-write memory
Roundoff errors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employing standard floating point units (FPUs), RAMs, and custom VLSI chips. It has been designed for use in an IBM PC/AT environment.< >
DOI:10.1109/ASIC.1992.270201