PLA test pattern generation with orthogonal transform

PLA test pattern generation with orthogonal transform

It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Riege, M.W., Wolter, S., Anheier, W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Boolean functions
Ducts
Equations
Hamming weight
Programmable logic arrays
Test pattern generators
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the authors' work is a method (as a part of fault simulation), which speeds up the process of test pattern generation for regular structures as PLAs, ROMs, RAMs and which also reduces time and storage complexity.< >
DOI:10.1109/MT.1993.263156