Status of the silicon strip high-rate FASTBUS readout system

A system to collect and process data at high rate, 53 MHz, from a silicon microstrip detector has been developed. The system is implemented using the FASTBUS standard and modularized at the board level in 128 channel increments. The system includes the following features: zero dead time readout for average trigger rate as high as 1 MHz; pipelined triggers and event readout; programmable data delay of up to 4.8 mu s; FASTBUS system readout; histogram readout option; and multiple high-speed bipolar process ASICs (application-specific integrated circuits). A general block diagram of data flow for the SSD (silicon strip detector) readout is provided. All the modules used for the SSD readout were tested individually to satisfy single board test requirements. Attention is given to SSD hardware for E771, a fixed target experiment designed to study the production of B hadrons by an 800 GeV/c proton beam.< >