1 mu m CMOS gate array radiation hardened technology
A 1 mu m radiation hardened ASIC gate array HCMOS technology is introduced which has a total dose specification of 3 Mrads(Si). This is based on both X-ray and Co60 gamma ray radiation test results at both the device and circuit level. Transistor threshold shifts of less than 0.45 volts are observed...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A 1 mu m radiation hardened ASIC gate array HCMOS technology is introduced which has a total dose specification of 3 Mrads(Si). This is based on both X-ray and Co60 gamma ray radiation test results at both the device and circuit level. Transistor threshold shifts of less than 0.45 volts are observed for both N and P channel devices in both on and off bias configurations up to a total dose of 5 Mrad. Also presented are circuit data including RAMs, and ring oscillator data illustrating the radiation tolerance of this technology. The circuit was functional with little additional degradation up to the maximum total dose level tested of 15 Mrad (Si). Single event cross section data gives a threshold LET on this technology of 52 MeV-cm2/mg using 254 MeV Ni and 320 MeV Au. Dose rate data on this technology gives an upset threshold level greater than 1E9 rads (Si)/sec. No SEE latch-up is observed for LET values measured up to 200 MeV-cm2/mg.< > |
---|---|
DOI: | 10.1109/REDW.1992.247322 |