Functional block design using VHDL simulation and synthesis

Functional block design using VHDL simulation and synthesis

This is a case study comparison between traditional and VHDL design methods of a small sized logic module (1500 gates). The areas where design cycle improvements and gate count reductions were realized are discussed as well as VHDL development strategies undertaken to reduce the impact of the design...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Weber, D.M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
Clocks
Computational modeling
Design methodology
Libraries
Logic design
Logic gates
Microelectronics
Springs
Testing
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Beschreibung
Zusammenfassung:This is a case study comparison between traditional and VHDL design methods of a small sized logic module (1500 gates). The areas where design cycle improvements and gate count reductions were realized are discussed as well as VHDL development strategies undertaken to reduce the impact of the design tools' limitations.< >
DOI:10.1109/ASIC.1991.242929